This application relies for priority upon Korean Patent Application No. 2001-55949, filed on Sep. 11, 2001, the contents of which are herein incorporated by reference in their entirety.
The present invention relates to a semiconductor memory device having a redundancy function. Also the invention relates to a semiconductor memory device to enhance a data access speed.
As a memory unit, a memory cell must stably store data that is processed in a system. Accordingly, there is a requirement for a procedure to test respective memory cells.
A redundancy circuit is a spare circuit, built into a memory device, for replacing defective cells with redundant memory cells. When an external address addressing a defective cell is input, the redundancy circuit disables a wordline organically connected to the defective cell and accesses a redundancy memory cell corresponding to the defective cell.
A semiconductor memory device must have a function to be instantly responsive to a central processing unit (CPU) speed, which is the most ideal requirement of system users. What is needed for having that function is to reduce the load of respective signal lines for transmitting a data access signal. Japan Laid-Open Application No. 7-182892 (filed on Dec. 22, 1993) discloses a semiconductor memory device having a hierarchical row decoder coupled to a main wordline, which can repair a defect without an increase in the number of redundancy main wordlines and occupy a minimal circuit area. Japan Laid-Open Application No. 8-340089 (filed on Mar. 2, 1995) discloses a DRAM device which can achieve a high speed by lowering the resistance of metal interconnections. Japan Laid-Open Application No. 10-308091 (filed on Mar. 2, 1997) discloses a semiconductor memory device which can suppress increase in the power consumption and achieve a high speed and a smaller occupied area while keeping the advantages of a hierarchical wordline. Japan Laid-Open Application No. 10-320979 (filed on Apr. 14, 1998) discloses a semiconductor memory device which can enhance a transmission speed and improve an integration level by shortening interconnections. U.S. Pat. No. 5,764,585 (filed on Jun. 7, 1996) discloses a DRAM device having a plurality of main row decoders each being coupled to one main wordline, and a plurality of sub-row decoders each being coupled to the one main wordline and a plurality of sub-wordlines, which can enhance an access speed of the device by reducing the load of the main row decoders. These above prior art devices are oriented toward a high speed by improving a chip layout,
Referring now to FIG. 1, a conventional DRAM device includes a plurality of memory cell arrays 10, 12, and 14 having a plurality of memory cells, a main row decoder 16, a plurality of main wordlines MWL0-MWL63, a predecoder 30, an address program circuit 32, a redundancy main wordline RMWL, sub-row decoders ah, and redundancy sub-row decoders i-p. Now, wordlines crossing over a plurality of memory cell arrays and their drivers are described in detail below. For reference, an external address used in the following discussion is XA0-XA8.
The main row decoder 16 activates one of 64 main wordlines MWL0-MWL63 according to an external row address XA3-XA8. Each of the main wordlines MWL0-MWL63 is connected to one side of the main row decoder 16 and is horizontally arranged over the memory cell arrays 10, 12, and 14. Each of sub-row decoders a, c, e, and g is disposed between the memory cell arrays 12 and 14, and is connected to a main wordline through a corresponding one of sub-wordlines SW0, SW2, SW4, and SW6 crossing over the memory cell array 12 and 14. Each of sub-row decoders b, d, f, and h is disposed between the memory cell arrays 10 and 12, and is connected to a main wordline through a corresponding one of sub-wordlines SW1, SW3, SW5, and SW7 crossing over the cell arrays 10 and 12.
The predecoder 30 activates one of eight predecoding lines SWPD0-SWPD7 according to an external row address XA0-XA2. Each of the predecoding lines SWPD0-SWPD7 is horizontally arranged over the memory cell arrays 10, 12, and 14 and is vertically arranged therebetween, coupling each of corresponding sub-row decoders a-h to one side of the predecoder 30. In other words, each of the predecoding lines SWPD0-SWPD7 is coupled to 64 sub-row decoders.
The address program circuit 32 receives the same address XA3-XA8 as an external address inputted to the main row decoder 16 during a repair operation, activating a redundancy main wordline RMWL. The redundancy main wordline RMWL is coupled to one side of the address program circuit 32 and is horizontally arranged over the memory cell arrays 12-14. Each of redundancy sub-row decoders i, k, m, and l is disposed between the memory cell arrays 12 and 14, and couples a corresponding one of redundancy sub-wordlines RSWL0, RSWL2, RSWL4, and RSWL 6 to the redundancy main wordline RMWL. Each of redundancy row decoders j, l, n, and p is disposed between the memory cell arrays 10 and 11, and couples a corresponding one of redundancy sub-wordlines RSWL1, RSWL3, RSWL5, and RSWL7 to the redundancy main wordline RMWL.
The operations of the above semiconductor memory device are now described in detail. Each of the main wordlines MWL0-MWL63 is activated according to the combination of external row addresses XA3-XA8. For example, when all external row addresses XA3-XA8 inputted to the main row decoder 16 are xe2x80x980xe2x80x99 (i.e., xe2x80x98000000xe2x80x99), only the main wordline MWL0 is activated and the others, MWL1-MWL63, are inactive.
The predecoder 30 activates one of eight predecoding lines SWPD0-SWPD7 according to an external row address XA0-XA2. For example, when all row addresses XA0-XA2 are xe2x80x980xe2x80x99 (i.e., xe2x80x98000xe2x80x99), the predecoding line SWPD0 is activated and the other predecoding lines SWPD1-SWPD7 are inactive.
As previously described, each of the sub-row decoders a-h is coupled to one of the main wordlines MWL0-MWL63 through a corresponding sub-wordline. Therefore, each of the sub-row decoders a-h is activated when both a main wordline and a predecoding line, which are organically coupled to each other, are activated. As described in the example above, when the 0th main wordline MWL0 and the 0th predecoding line are activated, only the sub-row decoder xe2x80x9caxe2x80x9d is activated. Therefore, the sub-row decoder xe2x80x9caxe2x80x9d activates memory cells coupled to the sub-wordline SW0.
The most ideal case is that a predecoding signal on the predecoding line SWPD0 is supplied to only the sub-row decoder xe2x80x9caxe2x80x9d coupled to the activated 0th main wordline MWL0. As shown in FIG. 1, however, the predecoding signal is supplied to all the sub-row decoders xe2x80x9caxe2x80x9d coupled to the 63 main wordlines MWL1-MWL63 as well as the activated main wordline MWL0 (i.e., the predecoding signal is supplied to all the 64 sub-row decoders xe2x80x9caxe2x80x9d), which becomes a load of the predecoding line SWPD0. From the standpoint of a signal, the data access signal on the predecoding line is subjected to a considerable physical resistance when it is supplied to the final cell. Therefore, the data access speed of the conventional memory device is reduced.
A repair is needed when a defective cell is created by various causes during a wafer fabricating process. When an external address for accessing a defective cell is inputted, a redundancy circuit disables a wordline coupled to a defective cell and enables a redundancy wordline. The conventional memory device of FIG. 1 carries out the repair with a main wordline unit. For example, when there are defective cells coupled to the sub-wordline SWL1 among cells in the memory cell array 12, operations of the memory device are described below.
As mentioned above, the sub-wordline SWL1 is activated when the main wordline MWL0 and the predecoding line SWPD1 are activated, i.e., an external address is xe2x80x98001000000xe2x80x99. Therefore, when an address XA0-XA8 (i.e., xe2x80x98001000000xe2x80x99) for selecting a sub-wordline SWL1 coupled to a defective cell is inputted, an address program circuit 32 disables the main row decoder 16 and activates a corresponding redundancy main wordline RMWL and a predecoding line SWPD1. As a result, all memory cells coupled to the 0th main wordline MWL0 are replaced by a redundancy main wordline RWML.
FIG. 2 illustrates a partial circuit construction of a main row decoder 16 associated with a 0th main wordline MWL0 and a partial circuit construction of a predecoder 30 associated with a 0th predecoding line SWPD0.
Referring now to FIG. 2, an address program circuit 32 compares an externally inputted row address XA3-XA8 with an address stored therein. According to the comparing result, the address program circuit 32 generates a redundancy enable signal RED_E indicating a normal mode or a repair mode. That is, if the externally inputted row address XA3-XA8 match up to the address stored in the address program circuit 32, the control signal becomes high (i.e., logic xe2x80x981xe2x80x99) to enter a repair mode. Otherwise, the control signal becomes low (i.e., logic xe2x80x980xe2x80x99) to exhibit a normal mode.
Components for activating a 0th main wordline MWL0 in a main row decoder 16 are a decoder 40, an inverter 44, and a buffer 45. Since components for activating the other wordlines MWL1-MWL63 are identical to the components for activating the 0th main wordline MWL0, only a circuit construction associated with the 0th main wordline MWL0 is illustrated and described at this time. The decoder 40 has NAND gates 41-43 and outputs a signal for activating the 0th main wordline MWL0 when all the external row addresses XA3-XA8 are low (i.e., xe2x80x98000000xe2x80x99) while a redundancy enable signal RED_E outputted from an address program circuit 32 is high. The buffer 45 converts the level of a signal outputted from the decoder 40 into the level suitable for driving the main wordline MWL0, and outputs the signal having the converted level.
Components for activating a 0th predecoding line SWPD0 in the predecoder 30 are an AND gate 51 and a buffer 52. Since components for activating the others SWPD0-SWPD7 are identical to the components for activating the 0th predecoding line SWPD0, only a circuit construction associated with the 0th predecoding line SWPD0 is illustrated and described at this time. The AND gate 51 outputs a signal for driving the predecoding line SWPD0 when the address XA0-XA2 is xe2x80x98000xe2x80x99. The buffer 52 converts the level of a signal outputted from the decoder 51 into the level suitable for driving the predecoding line SWPD0, and outputs the signal having the suitable level.
A buffer 60 converts the level of a redundancy enable signal RED_E outputted from the address program circuit 32 into the level suitable for driving the redundancy main wordline RMWL, and outputs the signal having the suitable level. Also the buffer 60 may be built in the address program circuit 32.
The conventional memory device having the foregoing structure carries out a normal mode when the control signal RED_E outputted from the address program circuit 32 is low. When the control signal RED_E is high, the conventional memory device carries out a repair mode where the redundancy main wordline RMWL is activated.
Unfortunately, even when only one of sub-wordlines coupled to one main wordline fails, all the sub-wordlines must be replaced by redundancy sub-wordlines in the repair mode. That is, a repair is performed with a wordline unit. Accordingly, a redundancy flexibility is reduced and a circuit area is increased.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need for a semiconductor memory device which realizes a high-speed operation by alleviating the load of a predecoding line. There is also a need for a semiconductor memory device to enhance a redundancy flexibility. What is also needed is a semiconductor memory device where circuit areas are reduced.
Accordingly, a semiconductor memory device is provided that includes at least one main wordline, a plurality of sub-wordlines corresponding to the main wordline, a plurality of main memory cells each being coupled to the sub-wordlines, a main wordline selector for activating the main wordline according to an external address, at least one redundancy sub-wordline, a plurality of redundancy sub-wordlines corresponding to the redundancy main wordline, a plurality of redundancy memory cells each being coupled to the redundancy sub-wordlines, a redundancy control circuit for disabling the main wordline selector when among the sub-wordlines, a sub-wordline to which a defective memory cell is coupled is addressed, and for controlling the sub-wordline to be replaced by the redundancy main wordline.
Beneficially, the number of the redundancy sub-wordlines coupled to the redundancy main wordline is smaller than the number of the sub-wordlines coupled to the main wordline. The redundancy control circuit enables the main wordline selector when among the sub-wordlines, a sub-wordline to which a normal main memory cell is coupled is addressed.
In one embodiment the redundancy control circuit has at least fuse circuit that stores a row address of the defective main memory cell and compares the stored address with an externally inputted address. If the addresses match up to each other, the fuse circuit generates a redundancy enable signal. The main wordline selector is enabled/disabled according to the redundancy enable signal.